Voltage Quadrupler for Silicon Photomultiplier (XRF scintillator-detector)

 A Silicon PhotoMultiplier (SiPM) requires about 25-30V to bias it into its avalanche-gain region, so some kind of voltage step-up circuit is needed to boost the power supply voltage.  My current electronics use +/- 10 volts so I need a voltage quadrupler, followed by a low-noise voltage voltage regulator.

I had experienced some noise-injection problems from the boost circuit used in the PocketGeiger, probably from the inductor.  It has to run a noticeable amount of current through the switching regulator's inductor because it also is used to boost 5V to the 9V needed to run the other electronics.  For this reason I have decided to try a charge pump-based voltage multiplier.  This type of circuit can't supply a large current, but the average current drawn by the SiPM will be very small so it should work OK.

I went with a Dickson-style voltage multiplier that uses two inputs that switch between 0 and +10.  The two inputs are 180 degrees out of phase, so a CMOS buffer would work well for this.  Here's an LTSpice simulation of the voltage multiplier:

Due to the relatively small capacitors it takes awhile to come up to its full voltage output.  The simulation was done using 1N914 diodes to get an idea of what the actual voltage output would be, because the voltage drop across each diode reduces the output voltage somewhat.

Since the in-phase and out-of-phase inputs should be balanced for best performance, the oscillator in my actual voltage multiplier needs to have a 50:50 duty cycle.  But this isn't all that easy to achieve.  Most CMOS oscillators based on inverters do NOT have a 50:50 duty cycle.  The other thing I didn't like is that the "best" oscillator I found uses 3 inverters, which used up more gates than I wanted -- producing an unbalanced drive capability for the two inputs to the charge pump.  I really needed a 2-gate oscillator with a guaranteed 50:50 duty cycle.

I recalled that the old transistor-based astable multivibrator produced a pretty good 50:50 duty cycle, so I designed one using two CMOS buffer/inverters, and simulated it using LTSpice.  The circuit initially didn't work because the Spice simulation uses buffers that are exactly the same -- there's no circuit imbalance to get the oscillator going.   I found it necessary to use a pulse generator to kick things off.  The pulse generator just outputs 1 pulse so it doesn't interfere with the simulation after it turns off.

Here's the result:

Since one of the outputs has a 50:50 duty cycle and everything is symmetric, the other output has a  50:50 duty cycle as well.  My initial choice for the R's and C's didn't oscillate at 10KHz, my target frequency, but it was easy to come up with a correction factor (based on the CD4049 Spice model).  That said, my calculations produced:  F = .417/(RC).  This was for a 10 volt supply voltage.  If I drop Vcc to 5V the frequency drops a bit -- to around 7.7KHz.  This is because the buffers' threshold voltage doesn't change as Vcc changes.  Based on the application, the frequency variation would be less of an issue than the fact that the voltage multiplier's output would drop by a factor of 4.  So....no big deal.

My circuit frees up an inverter, only uses one more component than the 3-gate oscillator and has a duty cycle that is much closer to 50:50.  Pretty much a win as far as I'm conerned.

The main variation in the duty factor would be due to tolerance-related variations in the external R's and C's.  Easily addressed by using parts with tighter tolerances, or adding a trimming resistor in series with one of the R's.  The latter approach is NOT preferred because trimmers are more expensive than resistors, and, of course, it's necessary to adjust the trimmer.  Expense would be a hobbyist AND commercial-product related concern, the time needed to adjust the trimmer would be an issue for a commercial product.